AN 922: Using the ECO Compilation Flow

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ID 683873
Date 3/31/2022
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Document Table of Contents
Document Table of Contents x
1. AN 922: Using the ECO Compilation Flow
1. AN 922: Using the ECO Compilation Flow x
1.1. Step 1: Open the Design Example Project 1.2. Step 2: Run the ECO Flow 1.3. Step 3: Implement Targeted ECOs 1.4. ECO Tcl Script Example 1.5. ECO Command Limitations 1.6. Document Revision History for AN 922: Using the ECO Compilation Flow
1.3. Step 3: Implement Targeted ECOs x
1.3.1. Modify the Lutmask 1.3.2. Change Routing Connections 1.3.3. Tie Off Input Port to GND 1.3.4. Modify Slew Rate, Current Strength, and Delay Chain 1.3.5. Place A Node in a New Location 1.3.6. Create a Wire LUT Atom
1.3.6. Create a Wire LUT Atom x
1.3.6.1. Running Incremental Flow with Signal Probe
1. AN 922: Using the ECO Compilation Flow

1. AN 922: Using the ECO Compilation Flow

In a typical FPGA project development cycle, the specification of the programmable logic portion of the design can change during the design process. The Intel® Quartus® Prime software supports these last-minute, targeted engineering change orders (ECOs), even after full compilation is complete. This application note demonstrates implementation of ECO's with an example design.

ECOs typically occur during the design verification stage. For example, during verification you may determine that the design requires a small change, such as a netlist connection change, correcting a LUT logic error, or placing a node in a new location. Implementing an ECO change, rather than changing RTL and fully recompiling the design, requires significantly less time, and changes only the affected logic.

You specify the ECO commands in a Tcl script using the ::quartus::eco package.

Table 1.  ECO Command Quick Reference
ECO Change ECO Commands
Route 
make_connection -from <src> -to <dst> -port <port>
remove_connection -from <src> -to <dst> -port <port>
Tie-Off 
make_connection –tieoff <VCC/GND> -to <node> -port <port>
Lutmask 
modify_lutmask -to <node> [-eqn <lut equation>] [-mask 0x00]
Slew Rate 
modify_io_slew_rate <value> -to <pin_name>
Current Strength 
modify_io_current_strength <value> -to <pin_name>
Delay Chains 
modify_io_delay_chain <value> -type <io_type> -to <pin_name>
Update MIF 
update_mif_files
IOPLL Ref Clock ( Intel® Stratix® 10 devices only) 
adjust_pll_refclk -to <pll name> -refclk <freq>
Create New Node 
create_new_node -type <LUT|FF> -name <name>
Remove Node 
remove_node -name <name>
Place Node 
place_node -name <name> [-location <location>]
Unplace Node 
unplace_node -name <name>
Create Wirelut 
create_wirelut -from <src> -to <dst> -port <port> [-location <location>]

The activities of this application note are divided into the following sections:

Note: The Intel® Quartus® Prime Pro Edition software supports ECOs only for Intel® Stratix® 10 and Intel® Agilex™ devices.

Section Content
Step 1: Open the Design Example Project
Step 2: Run the ECO Flow
Step 3: Implement Targeted ECOs
ECO Tcl Script Example
ECO Command Limitations
Document Revision History for AN 922: Using the ECO Compilation Flow

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