NiosII_stratixII_2s60_RoHS_TSE_SGDMA_sopc

generated 2009.05.26.15:40:04

Overview

  clk  NiosII_stratixII_2s60_RoHS_TSE_SGDMA_sopc
  clk_to_tse_pll 
   lcd_display
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
   button_pio
 in_port  
 out_port  
 out_port  
   ddr_sdram_0
 write_clk  
 clk_to_sdram  
 clk_to_sdram_n  
 ddr_cs_n  
 ddr_cke  
 ddr_a  
 ddr_ba  
 ddr_ras_n  
 ddr_cas_n  
 ddr_we_n  
 ddr_dq  
 ddr_dqs  
 ddr_dm  
 dqs_delay_ctrl  
 stratix_dll_control  
 dqsupdate  
   tse_mac
 gm_rx_d  
 gm_rx_dv  
 gm_rx_err  
 gm_tx_d  
 gm_tx_en  
 gm_tx_err  
 m_rx_d  
 m_rx_en  
 m_rx_err  
 m_tx_d  
 m_tx_en  
 m_tx_err  
 m_rx_col  
 m_rx_crs  
 tx_clk  
 rx_clk  
 set_10  
 set_1000  
 ena_10  
 eth_mode  
 mdio_out  
 mdio_oen  
 mdio_in  
 mdc  
   reconfig_request_pio
 bidir_port  
 rxd  
 txd  
Processor
   cpu Nios II 9.0
Peripherals
   pll altera_avalon_pll 9.0
   cpu altera_nios2 9.0
   ext_flash_enet_bus altera_avalon_tri_state_bridge 9.0
   sys_clk_timer altera_avalon_timer 9.0
   jtag_uart altera_avalon_jtag_uart 9.0
   high_res_timer altera_avalon_timer 9.0
   lcd_display altera_avalon_lcd_16207 9.0
   button_pio altera_avalon_pio 9.0
   led_pio altera_avalon_pio 9.0
   seven_seg_pio altera_avalon_pio 9.0
   ext_ssram_bus altera_avalon_tri_state_bridge 9.0
   ddr_sdram_0 ddr_sdram_component_classic 9.0
   sgdma_tx altera_avalon_sgdma 9.0
   tse_mac triple_speed_ethernet 9.0
   sgdma_rx altera_avalon_sgdma 9.0
   descriptor_memory altera_avalon_onchip_memory2 9.0
   tse_pll altera_avalon_pll 9.0
   packet_memory altera_avalon_onchip_memory2 9.0
   pipeline_bridge altera_avalon_pipeline_bridge 9.0
   reconfig_request_pio altera_avalon_pio 9.0
   uart1 altera_avalon_uart 9.0
cpu sgdma_tx sgdma_rx
 instruction_master  data_master  descriptor_read  descriptor_write  m_read  descriptor_read  descriptor_write  m_write
  pll
s1  0x07001000 0x07001000
  cpu
jtag_debug_module  0x07000000 0x07000000
  sys_clk_timer
s1  0x07001060 0x07001060
  jtag_uart
avalon_jtag_slave  0x070010c0 0x070010c0
  high_res_timer
s1  0x07001040 0x07001040
  lcd_display
control_slave  0x07001080 0x07001080
  button_pio
s1  0x07001090 0x07001090
  led_pio
s1  0x070010a0 0x070010a0
  seven_seg_pio
s1  0x070010b0 0x070010b0
  ddr_sdram_0
s1  0x02000000 0x02000000 0x02000000 0x02000000
  sgdma_tx
csr  0x07000800 0x07000800
  tse_mac
control_port  0x08412000
  sgdma_rx
csr  0x07000c00 0x07000c00
  descriptor_memory
s1  0x08410000 0x08410000 0x08410000 0x08410000 0x08410000
  tse_pll
s1  0x07001020 0x07001020
  packet_memory
s1  0x08400000 s2  0x08400000 0x08400000
  reconfig_request_pio
s1  0x07001940 0x07001940
  uart1
s1  0x070018c0 0x070018c0

clk

clock_source v9.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
  

Software Assignments

(none)

pll

altera_avalon_pll v9.0
clk clk   pll
  inclk0
pipeline_bridge m1  
  s1
c0   ext_flash_enet_bus
  clk
c0   sys_clk_timer
  clk
c0   jtag_uart
  clk
c0   high_res_timer
  clk
c0   ext_flash
  clk
c0   lcd_display
  clk
c0   button_pio
  clk
c0   led_pio
  clk
c0   seven_seg_pio
  clk
c0   ext_ssram_bus
  clk
c0   ext_ssram
  clk
c0   ddr_sdram_0
  s1_clock
c0   cpu
  clk
c0   descriptor_memory
  clk1
c0   sgdma_rx
  clk
c0   sgdma_tx
  clk
c0   tse_mac
  receive_clock_connection
c0  
  transmit_clock_connection
c0  
  control_port_clock_connection
c0   packet_memory
  clk1
c0  
  clk2
c0   pipeline_bridge
  clk
c0   reconfig_request_pio
  clk
c0   uart1
  clk


Parameters

c0 tap c0 mult 3 div 1 phase 0 enabled true inputfreq 50000000 outputfreq 150000000
c1 tap c1 mult 3 div 1 phase 620 enabled true inputfreq 50000000 outputfreq 150000000
c2 tap c2 mult 3 div 1 phase -1667 enabled true inputfreq 50000000 outputfreq 150000000
c3 tap c3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c4 tap c4 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c5 tap c5 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c6 tap c6 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c7 tap c7 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c8 tap c8 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c9 tap c9 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
deviceFamily STRATIXII
e0 tap e0 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e1 tap e1 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e2 tap e2 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e3 tap e3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
inputClockFrequency 50000000
inputClockRate 50000000
lockedOutputPortOption Export
pfdenaInputPortOption Register
pllHdl -- megafunction wizard: %ALTPLL% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altpll -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.0" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "150.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "6" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "6" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "6" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "151.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "151.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "151.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.62000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpllpll.mif" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "620" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1667" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
resetInputPortOption Register
  

Software Assignments

ARESET "None"
PFDENA "None"
LOCKED "None"
PLLENA "None"
SCANCLK "None"
SCANDATA "None"
SCANREAD "None"
SCANWRITE "None"
SCANCLKENA "None"
SCANACLR "None"
SCANDATAOUT "None"
SCANDONE "None"
CONFIGUPDATE "None"
PHASECOUNTERSELECT "None"
PHASEDONE "None"
PHASEUPDOWN "None"
PHASESTEP "None"

cpu

altera_nios2 v9.0
pll c0   cpu
  clk
pipeline_bridge m1  
  jtag_debug_module
d_irq   sys_clk_timer
  irq
d_irq   jtag_uart
  irq
d_irq   high_res_timer
  irq
d_irq   button_pio
  irq
custom_instruction_master   bswap
  s1
custom_instruction_master   interrupt_vector
  interrupt_vector
instruction_master   ext_ssram_bus
  avalon_slave
data_master  
  avalon_slave
instruction_master   ddr_sdram_0
  s1
data_master  
  s1
data_master   descriptor_memory
  s1
d_irq   sgdma_rx
  csr_irq
d_irq   sgdma_tx
  csr_irq
data_master   tse_mac
  control_port
data_master   packet_memory
  s1
instruction_master   pipeline_bridge
  s1
data_master  
  s1
d_irq   uart1
  irq


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSetsPresent false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_numShadowRegisterSets 1
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_eicPresent false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_autoAssignNumShadowRegisterSets true
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave ext_flash.s1
resetOffset 0
muldiv_multiplierType DSPBlock
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _10
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _32768
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave ddr_sdram_0.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level4
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _32768
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 150000000
breakSlave cpu.jtag_debug_module
breakOffset 32
  

Software Assignments

CPU_IMPLEMENTATION "fast"
CPU_FREQ 150000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 32768
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 32768
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x2000020
RESET_ADDR 0x6000000
BREAK_ADDR 0x7000020
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 1
INST_ADDR_WIDTH 28
DATA_ADDR_WIDTH 28

ext_flash_enet_bus

altera_avalon_tri_state_bridge v9.0
pll c0   ext_flash_enet_bus
  clk
pipeline_bridge m1  
  avalon_slave
tristate_master   ext_flash
  s1


Parameters

registerIncomingSignals true
  

Software Assignments

(none)

sys_clk_timer

altera_avalon_timer v9.0
pll c0   sys_clk_timer
  clk
cpu d_irq  
  irq
pipeline_bridge m1  
  s1


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 20
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 150000000
timeoutPulseOutput false
timerPreset FULL_FEATURED
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 20
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 150000000u
LOAD_VALUE 2999999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 50u

jtag_uart

altera_avalon_jtag_uart v9.0
pll c0   jtag_uart
  clk
cpu d_irq  
  irq
pipeline_bridge m1  
  avalon_jtag_slave


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
writeBufferDepth 64
writeIRQThreshold 8
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

high_res_timer

altera_avalon_timer v9.0
pll c0   high_res_timer
  clk
cpu d_irq  
  irq
pipeline_bridge m1  
  s1


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 10.0
periodUnits USEC
resetOutput false
snapshot true
systemFrequency 150000000
timeoutPulseOutput false
timerPreset FULL_FEATURED
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 10.0
PERIOD_UNITS "us"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 150000000u
LOAD_VALUE 1499ULL
COUNTER_SIZE 32
MULT 1.0E-6
TICKS_PER_SEC 100000u

ext_flash

altera_avalon_cfi_flash v9.0
ext_flash_enet_bus tristate_master   ext_flash
  s1
pll c0  
  clk


Parameters

actualHoldTime 40.0
actualSetupTime 46.66666666666667
actualWaitTime 160.0
addressWidth 24
clockRate 150000000
corePreset AMD29LV128M123R_BYTE
dataWidth 8
holdTime 35
setupTime 45
sharedPorts s1/address,s1/data
timingUnits NS
waitTime 160
  

Software Assignments

SETUP_VALUE 45
WAIT_VALUE 160
HOLD_VALUE 35
TIMING_UNITS "ns"
SIZE 16777216u

lcd_display

altera_avalon_lcd_16207 v9.0
pll c0   lcd_display
  clk
pipeline_bridge m1  
  control_slave


Parameters

(none)
  

Software Assignments

(none)

button_pio

altera_avalon_pio v9.0
pll c0   button_pio
  clk
cpu d_irq  
  irq
pipeline_bridge m1  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType ANY
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 15
width 4
  

Software Assignments

DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0xf
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "EDGE"
FREQ 150000000u

led_pio

altera_avalon_pio v9.0
pll c0   led_pio
  clk
pipeline_bridge m1  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

seven_seg_pio

altera_avalon_pio v9.0
pll c0   seven_seg_pio
  clk
pipeline_bridge m1  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 16
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 16
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

bswap

altera_nios_custom_instr_bitswap v6.1
cpu custom_instruction_master   bswap
  s1


Parameters

(none)
  

Software Assignments

(none)

interrupt_vector

altera_nios_custom_instr_interrupt_vector v6.1
cpu custom_instruction_master   interrupt_vector
  interrupt_vector


Parameters

(none)
  

Software Assignments

(none)

ext_ssram_bus

altera_avalon_tri_state_bridge v9.0
cpu instruction_master   ext_ssram_bus
  avalon_slave
data_master  
  avalon_slave
pll c0  
  clk
sgdma_rx m_write  
  avalon_slave
sgdma_tx m_read  
  avalon_slave
tristate_master   ext_ssram
  s1


Parameters

registerIncomingSignals true
  

Software Assignments

(none)

ext_ssram

altera_avalon_cy7c1380_ssram v9.0
ext_ssram_bus tristate_master   ext_ssram
  s1
pll c0  
  clk


Parameters

readLatency 3
sharedPorts s1/address,s1/data
simMakeModel true
size 2
  

Software Assignments

SRAM_MEMORY_SIZE 2
SRAM_MEMORY_UNITS 1048576
SSRAM_DATA_WIDTH 32
SSRAM_READ_LATENCY 3

ddr_sdram_0

ddr_sdram_component_classic v9.0
cpu instruction_master   ddr_sdram_0
  s1
data_master  
  s1
pll c0  
  s1_clock
sgdma_rx m_write  
  s1
sgdma_tx m_read  
  s1


Parameters

instancePTF MODULE ddr_sdram_0 { SLAVE s1 { PORT_WIRING { PORT clk { type = "clk"; width = "1"; direction = "input"; Is_Enabled = "1"; } PORT reset_n { type = "reset_n"; width = "1"; direction = "input"; Is_Enabled = "1"; } PORT local_read_req { type = "read"; width = "1"; direction = "input"; Is_Enabled = "1"; } PORT local_write_req { type = "write"; width = "1"; direction = "input"; Is_Enabled = "1"; } PORT local_addr { type = "address"; width = "23"; direction = "input"; Is_Enabled = "1"; } PORT local_wdata { type = "writedata"; width = "32"; direction = "input"; Is_Enabled = "1"; } PORT local_be { type = "byteenable"; width = "4"; direction = "input"; Is_Enabled = "1"; } PORT local_ready { type = "waitrequest_n"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT local_rdata { type = "readdata"; width = "32"; direction = "output"; Is_Enabled = "1"; } PORT local_rdata_valid { type = "readdatavalid"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT write_clk { type = "export"; width = "1"; direction = "input"; Is_Enabled = "1"; } PORT clk_to_sdram { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT clk_to_sdram_n { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT ddr_cs_n { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT ddr_cke { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT ddr_a { type = "export"; width = "13"; direction = "output"; Is_Enabled = "1"; } PORT ddr_ba { type = "export"; width = "2"; direction = "output"; Is_Enabled = "1"; } PORT ddr_ras_n { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT ddr_cas_n { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT ddr_we_n { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT ddr_dq { type = "export"; width = "16"; direction = "inout"; Is_Enabled = "1"; } PORT ddr_dqs { type = "export"; width = "2"; direction = "inout"; Is_Enabled = "1"; } PORT ddr_dm { type = "export"; width = "2"; direction = "output"; Is_Enabled = "1"; } PORT dqs_delay_ctrl { type = "export"; width = "6"; direction = "input"; Is_Enabled = "1"; } PORT stratix_dll_control { type = "export"; width = "1"; direction = "output"; Is_Enabled = "1"; } PORT dqsupdate { type = "export"; width = "1"; direction = "input"; Is_Enabled = "1"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Read_Wait_States = "peripheral_controlled"; Write_Wait_States = "peripheral_controlled"; Hold_Time = "0cycles"; Setup_Time = "0cycles"; Is_Printable_Device = "0"; Address_Alignment = "dynamic"; Well_Behaved_Waitrequest = "0"; Is_Nonvolatile_Storage = "0"; Address_Span = "33554432"; Read_Latency = "0"; Is_Memory_Device = "1"; Maximum_Pending_Read_Transactions = "16"; Minimum_Uninterrupted_Run_Length = "1"; Accepts_Internal_Connections = "1"; Write_Latency = "0"; Is_Flash = "0"; Data_Width = "32"; Address_Width = "23"; Maximum_Burst_Size = "1"; Register_Incoming_Signals = "0"; Register_Outgoing_Signals = "0"; Interleave_Bursts = "0"; Linewrap_Bursts = "1"; Burst_On_Burst_Boundaries_Only = "0"; Always_Burst_Max_Burst = "0"; Is_Big_Endian = "0"; Is_Enabled = "1"; Base_Address = "0x02000000"; Address_Group = "0"; } } class = "ddr_sdram_component"; class_version = "9.0"; iss_model_name = "altera_memory"; WIZARD_SCRIPT_ARGUMENTS { MEGACORE { title = "DDR SDRAM Controller"; version = "7.1"; build = "1"; iptb_version = "v1.3.0 build70"; format_version = "120"; NETLIST_SECTION { class = "altera.ipbu.flowbase.netlist.model.DDRSDRAMModel"; active_core = "ddr_sdram_0_auk_ddr_sdram"; STATIC_SECTION { PRIVATES { NAMESPACE parameterization { PRIVATE use_mem { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE gMEM_TYPE { value = "ddr_sdram"; type = "STRING"; enable = "1"; } PRIVATE projectname { value = "NiosII_stratixII_2s60_RoHS_TSE_SGDMA.qpf"; type = "STRING"; enable = "1"; } PRIVATE ddio_memory_clocks { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE new_wizard { value = "false"; type = "STRING"; enable = "1"; } PRIVATE local_burst_length { value = "1"; type = "INTEGER"; enable = "1"; } PRIVATE burst_length { value = "2"; type = "INTEGER"; enable = "1"; } PRIVATE odt_setting { value = "Disabled"; type = "STRING"; enable = "0"; } PRIVATE chip_selects_per_dimm { value = "1"; type = "INTEGER"; enable = "0"; } PRIVATE mig_device { value = "NONE"; type = "STRING"; enable = "1"; } PRIVATE mig_package { value = "NONE"; type = "STRING"; enable = "1"; } PRIVATE mig_speed_grade { value = "NONE"; type = "STRING"; enable = "1"; } PRIVATE mig_family { value = "NONE"; type = "STRING"; enable = "1"; } PRIVATE mig_defaultByteGroups { value = "default_value"; type = "STRING"; enable = "1"; } PRIVATE mig_ByteGroups { value = "default_value"; type = "STRING"; enable = "1"; } PRIVATE ADVANCED { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE include_x4_dm_pins { value = "1"; type = "BOOLEAN"; enable = "0"; } PRIVATE chipselects { value = "1"; type = "INTEGER"; enable = "0"; } PRIVATE LOCAL_WIDTH { value = "32"; type = "INTEGER"; enable = "1"; } PRIVATE bankbits { value = "2"; type = "INTEGER"; enable = "0"; } PRIVATE width { value = "16"; type = "INTEGER"; enable = "1"; } PRIVATE colbits { value = "9"; type = "INTEGER"; enable = "1"; } PRIVATE rowbits { value = "13"; type = "INTEGER"; enable = "1"; } PRIVATE dq_per_dqs { value = "8"; type = "INTEGER"; enable = "1"; } PRIVATE pch_bit { value = "10"; type = "INTEGER"; enable = "1"; } PRIVATE migratable_bytegroups { value = "0"; type = "BOOLEAN"; enable = "0"; } PRIVATE reg_dimm { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE pipeline_commands { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE enable_resynch_clk { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE enable_capture_clk { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE obj_hierarchy_path { value = "Automatically extracted by Quartus synthesis"; type = "STRING"; enable = "0"; } PRIVATE clock_pin_positive { value = "clk_to_sdram[0]"; type = "STRING"; enable = "1"; } PRIVATE clock_pin_negative { value = "clk_to_sdram_n[0]"; type = "STRING"; enable = "1"; } PRIVATE clock_fed_back_input { value = "fedback_clk_in"; type = "STRING"; enable = "0"; } PRIVATE run_add_constraints { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE run_verify_timing { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE generate_pll { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE update_top_level { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE manual_hierarchy_control { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE fed_back_clock { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE extra_pipeline_regs { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE pipeline_readdata { value = "Automatic"; type = "STRING"; enable = "0"; } PRIVATE addr_command { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE user_refresh { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE avalon { value = "1"; type = "BOOLEAN"; enable = "0"; } PRIVATE clock_speed { value = "50.0"; type = "STRING"; enable = "0"; } PRIVATE cas_latency { value = "2.5"; type = "STRING"; enable = "1"; } PRIVATE burst_type_int { value = "0"; type = "INTEGER"; enable = "1"; } PRIVATE burst_type { value = "sequential"; type = "STRING"; enable = "0"; } PRIVATE dll_enable { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE drive_strength { value = "normal"; type = "STRING"; enable = "1"; } PRIVATE ras_to_cas_delay { value = "2"; type = "INTEGER"; enable = "0"; } PRIVATE act_pch_time { value = "4"; type = "INTEGER"; enable = "0"; } PRIVATE write_to_read { value = "1"; type = "INTEGER"; enable = "1"; } PRIVATE write_recovery_time { value = "2"; type = "INTEGER"; enable = "0"; } PRIVATE row_precharge_time { value = "2"; type = "INTEGER"; enable = "0"; } PRIVATE refresh_command { value = "7"; type = "INTEGER"; enable = "0"; } PRIVATE load_mode { value = "2"; type = "INTEGER"; enable = "0"; } PRIVATE trefi { value = "389"; type = "INTEGER"; enable = "0"; } PRIVATE tinit_time { value = "9999"; type = "INTEGER"; enable = "0"; } PRIVATE trcd { value = "18"; type = "INTEGER"; enable = "1"; } PRIVATE tras { value = "42"; type = "INTEGER"; enable = "1"; } PRIVATE twr { value = "15"; type = "INTEGER"; enable = "1"; } PRIVATE trp { value = "18"; type = "INTEGER"; enable = "1"; } PRIVATE trfc { value = "72"; type = "INTEGER"; enable = "1"; } PRIVATE tmrd { value = "12"; type = "INTEGER"; enable = "1"; } PRIVATE user_trefi { value = "7.81"; type = "STRING"; enable = "1"; } PRIVATE user_tinit { value = "200.0"; type = "STRING"; enable = "1"; } PRIVATE use_project_timing_estimates { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE device { value = "EP2S60"; type = "STRING"; enable = "1"; } PRIVATE package { value = "F672"; type = "STRING"; enable = "1"; } PRIVATE speed_grade { value = "C5"; type = "STRING"; enable = "1"; } PRIVATE top_level { value = "ddr_sdram_0_debug_design"; type = "STRING"; enable = "1"; } PRIVATE pin_prefix { value = "ddr_"; type = "STRING"; enable = "1"; } PRIVATE family { value = "Stratix II"; type = "STRING"; enable = "1"; } PRIVATE resynch_cycle { value = "0"; type = "INTEGER"; enable = "0"; } PRIVATE intermediate_resynch { value = "1"; type = "BOOLEAN"; enable = "0"; } PRIVATE resynch_edge { value = "rising"; type = "STRING"; enable = "0"; } PRIVATE capture_edge { value = "rising"; type = "STRING"; enable = "1"; } PRIVATE resync_phase { value = "270"; type = "INTEGER"; enable = "0"; } PRIVATE fedback_resync_phase { value = "0"; type = "INTEGER"; enable = "0"; } PRIVATE capture_phase { value = "-1"; type = "INTEGER"; enable = "0"; } PRIVATE postamble_phase { value = "270"; type = "INTEGER"; enable = "0"; } PRIVATE stratixii_dqs_phase { value = "6000"; type = "INTEGER"; enable = "1"; } PRIVATE stratixii_dll_delay_buffer_mode { value = "low"; type = "STRING"; enable = "1"; } PRIVATE stratixii_dll_delay_chain_length { value = "12"; type = "INTEGER"; enable = "1"; } PRIVATE stratixii_dqs_out_mode { value = "delay_chain2"; type = "STRING"; enable = "1"; } PRIVATE enable_postamble_logic { value = "1"; type = "BOOLEAN"; enable = "0"; } PRIVATE stratix_dll_control { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE manual_pin_control { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE pf_pin_load_on_dq { value = "4"; type = "INTEGER"; enable = "0"; } PRIVATE pf_pin_load_on_cmd { value = "2"; type = "INTEGER"; enable = "0"; } PRIVATE pf_pin_load_on_clk { value = "2"; type = "INTEGER"; enable = "0"; } PRIVATE fed_back_clock_delay { value = "2000"; type = "INTEGER"; enable = "0"; } PRIVATE board_tpd_clock_trace_nom { value = "550"; type = "INTEGER"; enable = "0"; } PRIVATE board_tpd_dqs_trace_total_nom { value = "550"; type = "INTEGER"; enable = "0"; } PRIVATE board_pcb_delay_var_percent { value = "5"; type = "INTEGER"; enable = "0"; } PRIVATE board_tskew_data_group { value = "20"; type = "INTEGER"; enable = "0"; } PRIVATE memory_tDQSQ { value = "450"; type = "INTEGER"; enable = "1"; } PRIVATE memory_tQHS { value = "550"; type = "INTEGER"; enable = "1"; } PRIVATE memory_tDQSCK { value = "600"; type = "INTEGER"; enable = "1"; } PRIVATE memory_tAC { value = "700"; type = "INTEGER"; enable = "1"; } PRIVATE memory_fmax_at_cl5 { value = "0.0"; type = "STRING"; enable = "1"; } PRIVATE memory_fmax_at_cl4 { value = "0.0"; type = "STRING"; enable = "1"; } PRIVATE memory_fmax_at_cl3 { value = "166.6667"; type = "STRING"; enable = "1"; } PRIVATE memory_fmax_at_cl25 { value = "166.6667"; type = "STRING"; enable = "1"; } PRIVATE memory_fmax_at_cl2 { value = "133.3333"; type = "STRING"; enable = "1"; } PRIVATE memory_tCK_MAX { value = "13000"; type = "INTEGER"; enable = "1"; } PRIVATE memory_tDS { value = "450"; type = "INTEGER"; enable = "1"; } PRIVATE memory_tDH { value = "450"; type = "INTEGER"; enable = "1"; } PRIVATE memory_tdqss_min { value = "0.75"; type = "STRING"; enable = "1"; } PRIVATE memory_tdqss_max { value = "1.25"; type = "STRING"; enable = "1"; } PRIVATE byte_groups { value = "1T 0T"; type = "STRING"; enable = "1"; } PRIVATE override_resynch_script { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE override_capture_script { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE override_postamble_script { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE override_timings { value = "0"; type = "BOOLEAN"; enable = "1"; } PRIVATE postamble_cycle { value = "0"; type = "INTEGER"; enable = "0"; } PRIVATE postamble_edge { value = "rising"; type = "STRING"; enable = "0"; } PRIVATE inter_postamble { value = "1"; type = "BOOLEAN"; enable = "0"; } PRIVATE postamble_clock { value = "write_clk"; type = "STRING"; enable = "0"; } PRIVATE postamble_buffers { value = "0"; type = "INTEGER"; enable = "0"; } PRIVATE capture_clk { value = "dedicated"; type = "STRING"; enable = "1"; } PRIVATE board_name { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE device_maxwidth_name { value = "64"; type = "INTEGER"; enable = "1"; } PRIVATE Default_ByteGroups { value = "3T 2T 1T 0T 0B 1B 2B 3B"; type = "STRING"; enable = "1"; } PRIVATE Board_ByteGroups { value = "1T 0T"; type = "STRING"; enable = "1"; } PRIVATE board_maxwidth { value = "16"; type = "INTEGER"; enable = "1"; } PRIVATE memory_device { value = "Nios Development Board, Stratix II (EP2S60) RoHS"; type = "STRING"; enable = "1"; } PRIVATE resynch_clk { value = "write_clk"; type = "STRING"; enable = "0"; } PRIVATE pin_file { value = "none"; type = "STRING"; enable = "1"; } PRIVATE local_address_width { value = "23"; type = "INTEGER"; enable = "1"; } PRIVATE local_data_width { value = "32"; type = "INTEGER"; enable = "1"; } PRIVATE clock_pairs { value = "1"; type = "INTEGER"; enable = "0"; } } NAMESPACE symbol { } NAMESPACE simgen_enable { PRIVATE enabled { value = "1"; type = "BOOLEAN"; enable = "1"; } PRIVATE language { value = "Verilog HDL"; type = "STRING"; enable = "1"; } } NAMESPACE quartus_settings { PRIVATE DEVICE { value = "EP2S60F672C5"; type = "STRING"; enable = "1"; } PRIVATE FAMILY { value = "Stratix II"; type = "STRING"; enable = "1"; } } NAMESPACE generate { } NAMESPACE serializer { } } PORTS { } LIBRARIES { } } } } } SYSTEM_BUILDER_INFO { Is_Enabled = "1"; Clock_Source = "pll_c0_out"; Has_Clock = "1"; Instantiate_In_System_Module = "1"; Date_Modified = "--unknown--"; Default_Module_Name = "ddr_sdram"; Required_Device_Family = "STRATIXII,STRATIXIIGX,STRATIX,STRATIXGX,CYCLONEII,CYCLONE"; Pins_Assigned_Automatically = "1"; View { MESSAGES { } } } SIMULATION { DISPLAY { SIGNAL a { name = "reset_n"; radix = "hexadecimal"; format = "Logic"; } SIGNAL b { name = "clk"; radix = "hexadecimal"; format = "Logic"; } SIGNAL c { name = "write_clk"; radix = "hexadecimal"; format = "Logic"; } SIGNAL d { name = "clk_to_sdram"; radix = "hexadecimal"; format = "Logic"; } SIGNAL e { name = "clk_to_sdram_n"; radix = "hexadecimal"; format = "Logic"; } SIGNAL f { name = "local_addr"; radix = "hexadecimal"; format = "Logic"; } #SIGNAL g { name = "local_size"; radix = "hexadecimal"; format = "Logic";} #SIGNAL h { name = "local_burstbegin"; radix = "hexadecimal"; format = "Logic";} SIGNAL i { name = "local_read_req"; radix = "hexadecimal"; format = "Logic"; } SIGNAL j { name = "local_write_req"; radix = "hexadecimal"; format = "Logic"; } SIGNAL k { name = "local_ready"; radix = "hexadecimal"; format = "Logic"; } SIGNAL l { name = "local_wdata"; radix = "hexadecimal"; format = "Logic"; } SIGNAL m { name = "local_be"; radix = "hexadecimal"; format = "Logic"; } SIGNAL n { name = "local_rdata_valid"; radix = "hexadecimal"; format = "Logic"; } SIGNAL o { name = "local_rdata"; radix = "hexadecimal"; format = "Logic"; } SIGNAL p { name = "ddr_cs_n"; radix = "hexadecimal"; format = "Logic"; } SIGNAL q { name = "ddr_a"; radix = "hexadecimal"; format = "Logic"; } SIGNAL r { name = "ddr_ba"; radix = "hexadecimal"; format = "Logic"; } SIGNAL s { name = "ddr_ras_n"; radix = "hexadecimal"; format = "Logic"; } SIGNAL t { name = "ddr_cas_n"; radix = "hexadecimal"; format = "Logic"; } SIGNAL u { name = "ddr_we_n"; radix = "hexadecimal"; format = "Logic"; } SIGNAL v { name = "ddr_dm"; radix = "hexadecimal"; format = "Logic"; } SIGNAL w { name = "ddr_dq"; radix = "hexadecimal"; format = "Logic"; } SIGNAL x { name = "ddr_dqs"; radix = "hexadecimal"; format = "Logic"; } SIGNAL y { name = "ddr_cke"; radix = "hexadecimal"; format = "Logic"; } } } }
sharedPorts
  

Software Assignments

(none)

sgdma_tx

altera_avalon_sgdma v9.0
pll c0   sgdma_tx
  clk
cpu d_irq  
  csr_irq
pipeline_bridge m1  
  csr
descriptor_read   descriptor_memory
  s1
descriptor_write  
  s1
m_read   ext_ssram_bus
  avalon_slave
m_read   ddr_sdram_0
  s1
out   tse_mac
  transmit
m_read   packet_memory
  s2


Parameters

actualDataTransferFIFODepth 64
addressWidth 32
alwaysDoMaxBurst true
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 0
sourceErrorWidth 1
transferMode MEMORY_TO_STREAM
writeBurstcountWidth 4
  

Software Assignments

READ_BLOCK_DATA_WIDTH 32
WRITE_BLOCK_DATA_WIDTH 32
STREAM_DATA_WIDTH 32
ADDRESS_WIDTH 32
HAS_READ_BLOCK 1
HAS_WRITE_BLOCK 0
READ_BURSTCOUNT_WIDTH 4
WRITE_BURSTCOUNT_WIDTH 4
BURST_TRANSFER 0
ALWAYS_DO_MAX_BURST 1
DESCRIPTOR_READ_BURST 0
UNALIGNED_TRANSFER 0
CONTROL_SLAVE_DATA_WIDTH 32
CONTROL_SLAVE_ADDRESS_WIDTH 8
DESC_DATA_WIDTH 32
CHAIN_WRITEBACK_DATA_WIDTH 32
STATUS_TOKEN_DATA_WIDTH 24
BYTES_TO_TRANSFER_DATA_WIDTH 16
BURST_DATA_WIDTH 8
CONTROL_DATA_WIDTH 8
ATLANTIC_CHANNEL_DATA_WIDTH 4
COMMAND_FIFO_DATA_WIDTH 104
SYMBOLS_PER_BEAT 4
IN_ERROR_WIDTH 0
OUT_ERROR_WIDTH 1

tse_mac

triple_speed_ethernet v9.0
pll c0   tse_mac
  receive_clock_connection
c0  
  transmit_clock_connection
c0  
  control_port_clock_connection
cpu data_master  
  control_port
sgdma_tx out  
  transmit
receive   sgdma_rx
  in


Parameters

atlanticSinkClockRate 83333333
atlanticSinkClockSource pll
atlanticSourceClockRate 83333333
atlanticSourceClockSource pll
avalonSlaveClockRate 83333333
avalonSlaveClockSource pll
avalonStNeighbours {TRANSMIT=sgdma_tx, RECEIVE=sgdma_rx}
channel_count 1
core_variation MAC_ONLY
core_version 2304
crc32check16bit 0
crc32dwidth 8
crc32gendelay 6
crc32s1l2_extern false
cust_version 1
dataBitsPerSymbol 8
dev_version 2304
deviceFamily STRATIXII
eg_addr 10
eg_fifo 1024
ena_hash true
enable_alt_reconfig false
enable_clk_sharing false
enable_ena 32
enable_fifoless false
enable_gmii_loopback true
enable_hd_logic true
enable_mac_flow_ctrl false
enable_mac_txaddr_set true
enable_mac_vlan false
enable_maclite false
enable_magic_detect true
enable_multi_channel false
enable_pkt_class true
enable_pma false
enable_reg_sharing false
enable_sgmii false
enable_shift16 true
enable_sup_addr true
enable_use_internal_fifo true
export_calblkclk false
export_pwrdn false
ext_stat_cnt_ena false
gigeAdvanceMode false
ifGMII MII_GMII
ifPCSuseEmbeddedSerdes false
ing_addr 10
ing_fifo 1024
insert_ta true
maclite_gige false
max_channels 1
mdio_clk_div 40
phy_identifier 0
ramType AUTO
reset_level 1
sopcSystemTopLevelName NiosII_stratixII_2s60_RoHS_TSE_SGDMA_sopc
stat_cnt_ena true
timingAdapterName sgdma_rx
toolContext SOPC_BUILDER
transceiver_type GXB
uiEgFIFOSize 1024 x 32 Bits
uiHostClockFrequency 0
uiIngFIFOSize 1024 x 32 Bits
uiMACFIFO false
uiMACOptions false
uiMDIOFreq 0.0 MHz
uiMIIInterfaceOptions false
uiPCSInterface false
uiPCSInterfaceOptions false
useLvds false
useMAC true
useMDIO true
usePCS false
use_sync_reset false
  

Software Assignments

TRANSMIT "sgdma_tx"
RECEIVE "sgdma_rx"
TRANSMIT_FIFO_DEPTH 1024
RECEIVE_FIFO_DEPTH 1024
FIFO_WIDTH 32
ENABLE_MACLITE 0
MACLITE_GIGE 0
USE_MDIO 1
NUMBER_OF_CHANNEL 1
NUMBER_OF_MAC_MDIO_SHARED 1
IS_MULTICHANNEL_MAC 0
MDIO_SHARED 0
REGISTER_SHARED 0
PCS 0
PCS_SGMII 0
PCS_ID 0u

sgdma_rx

altera_avalon_sgdma v9.0
pll c0   sgdma_rx
  clk
cpu d_irq  
  csr_irq
tse_mac receive  
  in
pipeline_bridge m1  
  csr
descriptor_read   descriptor_memory
  s1
descriptor_write  
  s1
m_write   ext_ssram_bus
  avalon_slave
m_write   ddr_sdram_0
  s1
m_write   packet_memory
  s2


Parameters

actualDataTransferFIFODepth 64
addressWidth 32
alwaysDoMaxBurst true
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 6
sourceErrorWidth 0
transferMode STREAM_TO_MEMORY
writeBurstcountWidth 4
  

Software Assignments

READ_BLOCK_DATA_WIDTH 32
WRITE_BLOCK_DATA_WIDTH 32
STREAM_DATA_WIDTH 32
ADDRESS_WIDTH 32
HAS_READ_BLOCK 0
HAS_WRITE_BLOCK 1
READ_BURSTCOUNT_WIDTH 4
WRITE_BURSTCOUNT_WIDTH 4
BURST_TRANSFER 0
ALWAYS_DO_MAX_BURST 1
DESCRIPTOR_READ_BURST 0
UNALIGNED_TRANSFER 0
CONTROL_SLAVE_DATA_WIDTH 32
CONTROL_SLAVE_ADDRESS_WIDTH 8
DESC_DATA_WIDTH 32
CHAIN_WRITEBACK_DATA_WIDTH 32
STATUS_TOKEN_DATA_WIDTH 24
BYTES_TO_TRANSFER_DATA_WIDTH 16
BURST_DATA_WIDTH 8
CONTROL_DATA_WIDTH 8
ATLANTIC_CHANNEL_DATA_WIDTH 4
COMMAND_FIFO_DATA_WIDTH 104
SYMBOLS_PER_BEAT 4
IN_ERROR_WIDTH 6
OUT_ERROR_WIDTH 0

descriptor_memory

altera_avalon_onchip_memory2 v9.0
pll c0   descriptor_memory
  clk1
cpu data_master  
  s1
sgdma_rx descriptor_read  
  s1
descriptor_write  
  s1
sgdma_tx descriptor_read  
  s1
descriptor_write  
  s1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName descriptor_memory
instanceID NONE
memorySize 8192
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "descriptor_memory"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 8192u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

tse_pll

altera_avalon_pll v9.0
clk_to_tse_pll clk   tse_pll
  inclk0
pipeline_bridge m1  
  s1


Parameters

c0 tap c0 mult 5 div 2 phase 0 enabled true inputfreq 50000000 outputfreq 125000000
c1 tap c1 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c2 tap c2 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c3 tap c3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c4 tap c4 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c5 tap c5 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c6 tap c6 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c7 tap c7 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c8 tap c8 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c9 tap c9 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
deviceFamily STRATIXII
e0 tap e0 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e1 tap e1 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e2 tap e2 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e3 tap e3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
inputClockFrequency 50000000
inputClockRate 50000000
lockedOutputPortOption Export
pfdenaInputPortOption Register
pllHdl -- megafunction wizard: %ALTPLL% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altpll -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.0" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II" -- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" -- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT NUMERIC "0.0" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
resetInputPortOption Register
  

Software Assignments

ARESET "None"
PFDENA "None"
LOCKED "None"
PLLENA "None"
SCANCLK "None"
SCANDATA "None"
SCANREAD "None"
SCANWRITE "None"
SCANCLKENA "None"
SCANACLR "None"
SCANDATAOUT "None"
SCANDONE "None"
CONFIGUPDATE "None"
PHASECOUNTERSELECT "None"
PHASEDONE "None"
PHASEUPDOWN "None"
PHASESTEP "None"

clk_to_tse_pll

clock_source v9.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
  

Software Assignments

(none)

packet_memory

altera_avalon_onchip_memory2 v9.0
cpu data_master   packet_memory
  s1
sgdma_rx m_write  
  s2
sgdma_tx m_read  
  s2
pll c0  
  clk1
c0  
  clk2


Parameters

allowInSystemMemoryContentEditor false
blockType MRAM
dataWidth 32
dualPort true
initMemContent false
initializationFileName packet_memory
instanceID NONE
memorySize 65536
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "packet_memory"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "M-RAM"
WRITABLE 1
DUAL_PORT 1
SIZE_VALUE 65536u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "MRAM"
INIT_MEM_CONTENT 0
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

pipeline_bridge

altera_avalon_pipeline_bridge v9.0
cpu instruction_master   pipeline_bridge
  s1
data_master  
  s1
pll c0  
  clk
m1   sgdma_tx
  csr
m1   sgdma_rx
  csr
m1   cpu
  jtag_debug_module
m1   lcd_display
  control_slave
m1   button_pio
  s1
m1   led_pio
  s1
m1   seven_seg_pio
  s1
m1   pll
  s1
m1   tse_pll
  s1
m1   high_res_timer
  s1
m1   sys_clk_timer
  s1
m1   jtag_uart
  avalon_jtag_slave
m1   ext_flash_enet_bus
  avalon_slave
m1   reconfig_request_pio
  s1
m1   uart1
  s1


Parameters

burstEnable false
dataWidth 32
downstreamPipeline true
enableArbiterlock false
maxBurstSize 2
maximumPendingReadTransactions 5
slaveAddressWidth 23
upstreamPipeline true
waitrequestPipeline true
  

Software Assignments

(none)

reconfig_request_pio

altera_avalon_pio v9.0
pipeline_bridge m1   reconfig_request_pio
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

uart1

altera_avalon_uart v9.0
cpu d_irq   uart1
  irq
pipeline_bridge m1  
  s1
pll c0  
  clk


Parameters

baud 115200
baudError 0.01
clockRate 150000000
dataBits 8
fixedBaud true
parity NONE
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts false
useEopRegister false
  

Software Assignments

BAUD 115200
DATA_BITS 8
FIXED_BAUD 1
PARITY 'N'
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 0
USE_EOP_REGISTER 0
SIM_TRUE_BAUD 0
SIM_CHAR_STREAM ""
FREQ 150000000u

generation took 0.02 seconds
rendering took 6.62 seconds