Introduction This HardwareLibs project is meant as an example for using the I2C APIs. The project demonstrates the following I2C Flash API features: - Communication with NHD-0216K3Z-NSW-BBW-V3 LCD screen (master write) - i2c_demo_master_lcd() - Communication with 24LC32 EEPROM memory (master read and write) - i2c_demo_master_eeprom() - Communication between two I2C modules (master and slave read and write) - i2c_demo_master_slave() The project also demonstrates the following additional API features: - Using Global Timer to implement delays - Using Interrupts Note: This example was tested against SoC EDS 16.1b196. ==== Target Boards: - Altera Arria10 SoC Development Board rev C. Target I2C Devices: - NHD-0216K3Z-NSW-BBW-V3 LCD screen - 24LC32 EEPROM memory ==== Hardware Design: A hardware design was required for the master slave example, since only I2C0 is connected on the I2C bus on the Arria10 SoC boards. The hardware design is based on the GHRD (Golden Hardware Reference Design with the only modification that the I2C2 signals are connected to the I2C bus through the FPGA. This was possible because the FPGA has two pins connected to the board I2C bus. Note that the Bootloader was also re-generated and compiled for this hardware design. The Bootloader is ran by the debugger script before the program is started. The hardware design is contained in the folder named 'a10_soc_devkit_i2c_lpbk'. ==== Limitations: 1. Due to the fact that an (RT)OS was not used, the master slave example is limited to a buffer size of 64bits. This is because implementing a state machine to deal with interrupts and with the data flow would be cumbersome and not very helpful without and (RT)OS. ===== Source Files The following are descriptions of the source and header files contained in this project: i2c_demo_a10.{c,h} Contain the main, system initialization and cleanup, delay functions. i2c_demo_masterlcd_a10.c Contains the functions demonstrating communication with I2C LCD using master operation mode. i2c_demo_master_eeprom_a10.c Contains the functions demonstrating communication with I2C EEPROM using master operation mode. i2c_demo_master_slave_a10.c Contains the functions demonstrating communication between two I2C modules, one running as master and the other as slave. ===== Building the Example Before running the example, the target executable first needs to be built. 1. In DS-5, build the application: 1a. Switch to the C/C++ Perspective if not already in that perspective by selecting the menu: Window >> Open Perspective >> C/C++. 1b. In the "Project Explorer" panel, right-mouse-click "Altera-SoCFPGA-HardwareLib-I2C-A10-GNU" and select "Build Project". The Console panel (bottom of the UI) should detail the progress of the build and report any warnings or errors. ===== Running the Example 1. Configure the FPGA with the FPGA configuration file a10_soc_devkit_gpio/output_files/ghrd_10as066n2.sof This can be achieved by running the following commands from the Embedded Command Shell: cd quartus_pgm --no_banner --mode=jtag -o "p;a10_soc_devkit_i2c_lpbk/output_files/ghrd_10as066n2.sof" 2. Connect the USB to serial bridge to the host computer. 3. Connect the USB-BlasterII to the host computer. 4. Install the USB to serial bridge driver on the host computer if that driver is not already present. Consult documentation for the DevKit for instructions on installing the USB to serial bridge driver. 5. Install the USB-BlasterII driver on the host computer if that driver is not already present. Consult documentation for QuartusII for instructions on installing the USB-BlasterII driver. 6. In DS-5, configure the launch configuration. 6a. Select the menu: Run >> Debug Configurations... 6b. In the options on the left, expand "DS-5 Debugger" and select "Altera-SoCFPGA-HardwareLib-I2C-A10-GNU". 6c. In the "Connections" section near the bottom, click Browse. 6d. Select the appropriate USB-BlasterII to use. Multiple items will be presented if there is more than one USB-BlasterII connection attached to the host computer. 6e. Click "Apply" then "OK" to apply the USB-BlasterII selection. 6f. Click "Close" to close the Debug Configuration. Otherwise click "Debug" run the example in the debugger. Connecting to the target takes a moment to load the Bootloader, run the Bootloader, load the executable, and run executable. After the debug connection is established, the debugger will pause the execution at the main() function. Users can then set additional break points, step into, step out of, or step one line using the DS-5 debugger. Consult documentation for DS-5 for more information on debugging operations. ===== Sample output The address and size of the test buffers are randomly generated for each test, to help with wear levelling of the I2C EEPROM memory device. The following is a sample output: INFO: System Initialization. INFO: Setting up Global Timer. INFO: Using random seed = 0x10a64c8. INFO: I2C Demo Master LCD started. INFO: Init I2C module. INFO: Enable I2C module. INFO: Configuring I2C parameters. INFO: Current I2C speed = 32765 Hz. INFO: New I2C speed = 40000 Hz. INFO: Turning display on. INFO: Clearing screen. INFO: Turning cursor on. INFO: Printing text. INFO: Printing random number. INFO: Moving cursor to the 2nd line. INFO: Printing text. INFO: I2C Demo Master LCD succeeded. INFO: I2C Demo Master EEPROM started. INFO: Init I2C module. INFO: Enable I2C module. INFO: Configuring I2C parameters. INFO: Using I2C speed = 100000 Hz. INFO: Using random address = 0x0aa5, size = 252 bytes. INFO: Writing to EEPROM address 0x0aa5, size = 252 bytes. INFO: Writing single byte at address = 0x0aa5. INFO: Writing single byte at address = 0x0aa6. INFO: Writing single byte at address = 0x0aa7. INFO: Writing single byte at address = 0x0aa8. INFO: Writing single byte at address = 0x0aa9. INFO: Writing single byte at address = 0x0aaa. INFO: Writing single byte at address = 0x0aab. INFO: Writing single byte at address = 0x0aac. INFO: Writing single byte at address = 0x0aad. INFO: Writing single byte at address = 0x0aae. INFO: Writing single byte at address = 0x0aaf. INFO: Writing single byte at address = 0x0ab0. INFO: Writing single byte at address = 0x0ab1. INFO: Writing single byte at address = 0x0ab2. INFO: Writing single byte at address = 0x0ab3. INFO: Writing single byte at address = 0x0ab4. INFO: Writing single byte at address = 0x0ab5. INFO: Writing single byte at address = 0x0ab6. INFO: Writing single byte at address = 0x0ab7. INFO: Writing single byte at address = 0x0ab8. INFO: Writing single byte at address = 0x0ab9. INFO: Writing single byte at address = 0x0aba. INFO: Writing single byte at address = 0x0abb. INFO: Writing single byte at address = 0x0abc. INFO: Writing single byte at address = 0x0abd. INFO: Writing single byte at address = 0x0abe. INFO: Writing single byte at address = 0x0abf. INFO: Writing 32 byte page at address = 0x0ac0. INFO: Writing 32 byte page at address = 0x0ae0. INFO: Writing 32 byte page at address = 0x0b00. INFO: Writing 32 byte page at address = 0x0b20. INFO: Writing 32 byte page at address = 0x0b40. INFO: Writing 32 byte page at address = 0x0b60. INFO: Writing 32 byte page at address = 0x0b80. INFO: Writing single byte at address = 0x0ba0. INFO: Reading from EEPROM address 0x0aa5, size = 252 bytes. INFO: Setting EEPROM pointer address to 0x0aa5. INFO: Sequentially reading 252 bytes from EEPROM. INFO: Comparing written data with read back data. INFO: I2C Demo Master EEPROM succeeded. INFO: I2C demo master slave started. INFO: Setting up I2C interrupt. INFO: Init master I2C module. INFO: Init slave I2C module. TEST: Buffer size = 64. INFO: Master transmitting. INFO: Master receiving. INFO [ISR]: Reading data from bus ... INFO [ISR]: Writing 64 data item(s) to bus.. INFO: Comparing received data with transmitted data. TEST: Buffer size = 32. INFO: Master transmitting. INFO: Master receiving. INFO [ISR]: Reading data from bus ... INFO [ISR]: Writing 32 data item(s) to bus.. INFO: Comparing received data with transmitted data. INFO: Cleaning up master. INFO: Cleaning up slave. INFO: Cleaning up I2C interrupt. INFO: I2C demo master slave succeeded. INFO: System shutdown. RESULT: All tests successful.