sbcfg5

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA070

Offset: 0x70

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_period_dqstrk_ctrl_en

0x0

cfg_short_dqstrk_ctrl_en

0x0

sbcfg5 Fields

Bit Name Description Access Reset
1 cfg_period_dqstrk_ctrl_en
Set to 1 to enable controller to issue periodic DQS tracking
RW 0x0
0 cfg_short_dqstrk_ctrl_en
Set to 1 to enable controller controlled DQS short tracking, Set to 0 to enable sequencer controlled DQS short tracking
RW 0x0