High-k/Metal-Gate Stack and Its MOSFET Characteristics
We show experimental evidence of surface phonon scattering in the high-dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal–gate electrode is effective in screening phonon scattering in the high- dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal–gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel motilities to close to those of the conventional SiO2/poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high- metal–gate CMOS transistors with desirable threshold voltages.
The silicon industry has been scaling silicon dioxide (SiO ) aggressively for the past 15 years for low-power, high-performance CMOS transistor applications. Recently, SiO with physical thickness of 1.2 nm has been implemented in the 90-nm logic technology node. In addition, research transistors with 0.8-nm (physical thickness) SiO have been demonstrated in the laboratory. However, continual gate oxide scaling will require high- gate dielectric (being the dielectric constant) since the gate oxide leakage in SiO is increasing with reducing physical thickness and SiO will eventually run out of atoms for further scaling. The majority of the high-gate dielectrics investigated are Hf-based and Zr-based. Both poly-Si and metals are being evaluated as the gate electrodes for the high-gate dielectrics. There are many challenges reported in literature in replacing SiO with high-dielectrics for high-performance CMOS applications. It has been reported that Fermi-level pinning at the high-poly-Si transistors causes high threshold voltages in MOSFET transistors, resulting in poor transistor drive performance. It has also been reported that high-poly-Si transistors exhibit severely degraded channel mobility.
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