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High-Performance Computing for Silicon Design

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High-Performance Computing for Silicon Design

IT@Intel White Paper: Intel Information Technology High-Performance Computing, November 2009
Executive Overview
Designing Intel® microprocessors is extremely compute intensive. Tapeout is a final step in silicon design, and its computation demand is growing exponentially for each generation of silicon process technology. Intel IT adopted high-performance computing (HPC) to address this very large computational scale and realized significant improvements in computing performance, reliability, and cost.
To support the critical tapeout design stage for the first Intel 45-nm processors, we expected a 10x increase in compute scalability requirements, and we also needed to improve the stability of our environment. To meet these requirements, Intel IT developed an HPC environment optimized for tapeout. This was a pioneering application of HPC for silicon design. We treated the HPC environment as a holistic computing capability—ensuring all key components were well designed, integrated, and operationally balanced with no bottlenecks. We designed our HPC model to scale to meet future needs, with HPC generations aligned with successive generations of Intel® process technology.
The first-generation HPC environment (HPC-1), supporting 45-nm processor tapeout, included innovative approaches and technologies to increase scalability, such as:
• A parallel storage system providing 10x scalability compared with our previous system based on traditional file servers, together with high-speed backup.
• Large-memory compute servers based on a unique modular non-uniform memory access (NUMA) design, offering significant cost advantages. Significant solution integration engineering was required to bring these systems into production. Batch compute servers based on multi-core Intel® Xeon® processors, offering substantial performance increases.
• Optimization of our license server and job scheduler to handle thousands of simultaneous design jobs.

Read the full High-Performance Computing for Silicon Design White Paper.