Intel® E7501 Chipset Memory Controller Hub Datasheet
The Intel® E7501 chipset is targeted for the server market, both front-end and general-purpose, low- to mid-range. It is intended to be used with the Intel® Xeon® processor with 512-KByte L2 cache and the Intel® Xeon® processor with 533 MHz system bus. The Intel E7501 is also targeted for the applied-computing market. It is intended to be used with the Intel® Pentium® M processor with one Mbyte of L2 cache. The Intel E7501 chipset consists of three major components: the Intel® E7501 Chipset Memory Controller Hub (MCH), the Intel® I/O Controller Hub 3-S (Intel® ICH3-S), and the PCI/PCI-X 64-bit Hub 2.0 (P64H2). The MCH provides the processor system bus interface, memory controller, hub interface for legacy I/O, and three high-performance hub interfaces for PCI/PCI-X bus expansion.
This document describes the E7501 chipset MCH. The MCH signals, registers, DC electrical characteristics, ballout, package dimensions, and component testability are covered. The major functional blocks of the MCH are described. For detailed descriptions of the other chipset components, refer to the respective component’s datasheet. Information on platform design can be found in the Intel® Xeon® Processor and Intel® E7500/E7501 Chipset Compatible Platform Design Guide.
Read the full Intel® E7501 Chipset Memory Controller Hub Datasheet.