Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

The Intel® 5000X chipset is designed for systems based on the Dual-Core Intel® Xeon® 5000 sequence and supports a FSB frequency up to 1333 MTS. The Intel 5000X chipset contains two main components: Memory Controller Hub (MCH) for the host bridge and the I/O controller hub for the I/O subsystem. The Intel 5000X chipset uses the Intel® 631xESB/632xESB I/O Controller Hub for the I/O Controller Hub. This document is the datasheet for the Intel 5000X Memory Controller Hub Chipset(MCH) components.

The Intel 5000X chipset is packaged in a 1432 pin FCBGA package with pins on 1.092 mm (37 mil) centers. The overall package dimensions are 42.5 mm by 42.5 mm. The Intel 5000 Series chipset platform supports the Dual-Core Intel® Xeon® 5000 series (1066 MHz with 2 MB L2 cache on 65nm process in a 771-land, FC-LGA4 (Flip Chip Land Grid Array 4) package and the Dual-Core Intel® Xeon® 5100 series (1333 MHz with 4 MB shared L2 cache) on 65nm process in a 771-land, FC-LGA4 (Flip Chip Land Grid Array 4) package. This package uses the matching LGA771 socket. The surface mount, LGA771 socket supports Direct Socket Loading (DSL). The Dual-Core Intel Xeon 5000 sequence (1066/1333 MHz) returns a processor signature of 0F5xh where x is the stepping number when the CPUID instruction is executed with EAX=1. Note: Unless otherwise specified, the term processor in this document refers to the Dual-Core Intel Xeon 5000 sequence processors at both 1066 MHz with 2 MB L2 cache and 1333 MHz with 4 MB shared L2 cache on 65nm process in the 771-pin FC-LGA4 package.

Read the full Intel® 5000X Chipset Memory Controller Hub Datasheet.